1, Data selector
1. Detailed explanation of principle
-
What is a data selector?
According to the given input address code, the data selector selects a specified combinational logic circuit from a group of input signals to the output. Sometimes called a multiplexer or multiplexer. -
Basic definition of data selector
In the process of multi-channel data transmission, the circuit that can select any one of them according to needs is called data selector.
-
logic function
The logic function of the data selector is to select one path of data from multiple data as the output signal under the control of the address selection signal. -
classification
2-out-of-1, 4-out-of-1, 8-out-of-1 and 16-out-of-1 data selectors.
2. Working mode
In combination with the above figure, giving A1A0 a group of signals, such as 10, is equivalent to giving him a binary digit, and 2 is equivalent to gating the input terminal D2. At this time, the output y is the signal of D2, and Y outputs whatever D2 is.
| control | Selected output source | |
|---|---|---|
| A1 | A0 | Y |
| 0 | 0 | D0 |
| 0 | 1 | D1 |
| 1 | 0 | D2 |
| 1 | 1 | D3 |
2, Four digit data selector function verification
1. Verilog implements four bit selector
Write a simple four bit selector with Verilog
module multiplexer_s(
input clk ,
input rst_n ,
input din_a ,
input din_b ,
input din_c ,
input din_d ,
input [1:0] sel ,
output dout
);
//Signal definition
reg data_dout;
always @(posedge clk or negedge rst_n) begin
if(!rst_n)begin
data_dout <= 2'b00;
end
else begin
case(sel)
2'b00: data_dout <= din_a ;
2'b01: data_dout <= din_b ;
2'b10: data_dout <= din_c ;
2'b11: data_dout <= din_d ;
default:data_dout <= 2'b00 ;
endcase
end
end
assign dout = data_dout;
endmodule
Top level module
module multiplexer(
input clk ,
input rst_n ,
output dout
);
wire din_a ;
wire din_b ;
wire din_c ;
wire din_d ;
wire [1:0] sel ;
//Modular instantiation
multiplexer_s u_multiplexer
(
.din_a (din_a ) ,
.din_b (din_b ) ,
.din_c (din_c ) ,
.din_d (din_d ) ,
.sel (sel ) ,
.dout (dout ) ,
.rst_n (rst_n ) ,
.clk (clk )
);
endmodule
2. Create project
For detailed steps of project creation, please refer to this article:
Digital tube realizes stopwatch counting
After the project is created, import the four digit data selector source code into the project
Import the project file for full compilation
View RTL circuit diagram
3. Change system endogenous and probe
Click IP Catalog in the upper right corner of quartus or Tools → IP Catalog
Change ip
Expand the small window and click OK
Configure the values of source and probes, and then click generate HDl
Then click generate
When the generation is complete, click close
You can see the generated issp file in the prj folder
Locate the issp.v file in the file directory
Open the file and instantiate this part of the file into a four bit selector
module issp ( input wire [31:0] probe, // probes.probe output wire [31:0] source // sources.source );
Code of each part after instantiation
①multiplexer.v
module multiplexer(
input clk ,
input rst_n ,
output dout
);
wire din_a ;
wire din_b ;
wire din_c ;
wire din_d ;
wire [1:0] sel ;
//Modular instantiation
multiplexer_s u_multiplexer
(
.din_a (din_a ) ,
.din_b (din_b ) ,
.din_c (din_c ) ,
.din_d (din_d ) ,
.sel (sel ) ,
.dout (dout ) ,
.rst_n (rst_n ) ,
.clk (clk )
);
wire [31:0] probe ;
issp u_issp
(
.probe (probe ),
.source ({sel,din_a,din_b,din_c,din_d})
);
endmodule
Add the set issp entity to the project file
Compile the whole project
4. Logical analysis
[Tools]→[Signal Tap Logic Analyzer]
Connect to the development board and burn it first to ensure that the driver is normal
Select the driver used and download the file, and set the sampling clock and depth
Download File
Set the Clock and click the three small dots behind the Clock to display the interface shown in
Select Design Entry (all names) in the Filter drop-down box. Then click list
Select the sampling clock in the interface that appears again
Download the. sof file
Select Tools → In_System Source and Probes Editor
Download the. sof file
The interface as shown in the figure appears. Expand the source assignment to see the output changes
Click the run icon to see the following waveform in [Signal Tap Logic Analyzer]
Click the red box icon to perform self round trip analysis
The change of waveform can be observed by assigning corresponding values to source.
5. Functional verification
Schematic diagram of chip selection signal
The {} mode in {sel,din_a,din_b,din_c,din_d} is from high to low, and variables without specified bit width are not allowed in splicing.
According to this code block, verify its logical function:
case(sel)
2'b00: data_dout <= din_a ;
2'b01: data_dout <= din_b ;
2'b10: data_dout <= din_c ;
2'b11: data_dout <= din_d ;
default:data_dout <= 1'b0 ;
endcase
① When the chip selection signal sel is 00, data_out output din_a
② When the chip selection signal sel is 01, data_out output din_b
③ When the chip selection signal sel is 10, data_out output din_c
④ When the chip selection signal sel is 11, data_out output din_d
3, D trigger
1. Basic concepts
- D flip-flop is an information storage device with memory function and two stable states. It is not only the most basic logic unit constituting a variety of sequential circuits, but also an important unit circuit in digital logic circuits.
- The D flip-flop flips at the leading edge of the clock pulse CP (positive jump 0 → 1). The secondary state of the flip-flop depends on the state of the d end before the rising edge of the pulse of CP, that is, the secondary state = D. Therefore, it has two functions: setting 0 and setting 1. Since the circuit has the function of maintaining blocking during CP=1, the data state of D terminal changes during CP=1, which will not affect the output state of the trigger.
2. Working principle
SD and RD are connected to the input terminal of the basic RS trigger, which are preset and reset terminals respectively. The low level is effective. When SD=0 and RD=1, regardless of the state of input D, Q=1 and Q=0, that is, the trigger is set to 1; When SD=1 and RD=0, the state of the trigger is 0. SD and RD are usually called direct set 1 and set 0 terminals.
Workflow
- When CP=0, NAND gates G3 and G4 are blocked, their output Q3=Q4=1, and the state of the trigger remains unchanged. At the same time, since the feedback signals from Q3 to Q5 and Q4 to Q6 open the two doors, the input signals D, Q5=D, Q6=Q5 non = D non can be received;
- When CP changes from 0 to 1, the trigger flips. At this time, G3 and G4 are turned on, and the states of their inputs Q3 and Q4 are determined by the output states of G5 and G6. Q3=Q5 non = D non, Q4=Q6 non = D. According to the logic function of the basic RS trigger, Q=Q3, non = D;
4, D trigger function verification
1. Implementation of simple D trigger in Verilog
D trigger module
data_flip_flop.v
module data_flip_flop(
input clk ,//System clock
input rst_n ,//Reset signal
input en ,//Enable signal (cp)
input d ,//D trigger input
output q ,//Output q
output q_n //Output non-q
);
//Signal definition
reg dout_q ;//Output definition
always @(posedge clk or negedge rst_n) begin
if(~rst_n)begin
dout_q <= 0;
end
else if(en) begin
dout_q <= d;
end
else begin
dout_q <= 0;
end
end
assign q = dout_q ;
assign q_n = ~dout_q ;
endmodule
Top level module
data_flip_flop_top.v
module data_flip_flop_top(
input clk ,
output q ,
output q_n
);
//Signal definition
wire d ;
wire en ;
wire rst_n ;
//Modular instantiation
data_flip_flop u_data_flip_flop
(
.clk ( clk ),
.rst_n ( rst_n),
.en ( en ),
.d ( d ),
.q ( q ),
.q_n ( q_n )
);
endmodule
View the RTL schematic generated by Verilog
Click + to expand and view the structure of the circuit
2. Step brief solution (the detailed steps are the same as the data selector)
Configure ip, rename it and save it in the ip (intellectual property) directory
Change system endogenous and probe
Add the generated issp file to the project
Add as shown in
Instantiate this part of the code to the top-level module
module issp ( input wire [7:0] probe, // probes.probe output wire [7:0] source // sources.source );
Instantiated top-level module source code
module data_flip_flop_top(
input clk ,
output q ,
output q_n
);
//Signal definition
wire d ;
wire en ;
wire rst_n ;
wire [7:0] probe ;
//Modular instantiation
data_flip_flop u_data_flip_flop
(
.clk ( clk ),
.rst_n ( rst_n),
.en ( en ),
.d ( d ),
.q ( q ),
.q_n ( q_n )
);
issp u_issp
(
.source ( {rst_n,en,d} ) ,
.probe ( probe )
);
endmodule
3. Logical analysis
GIF dynamic diagram, show you the steps
Double click the blank interface to add a signal
Red indicates an error. The added wire signal needs to be changed
Right click select all and click delete again
Double click the blank again to add a signal
Add the signal as shown in the figure
In the endogenous probe editor, download the. sof file
In the [Tap] interface, operate once according to the arrow in the figure
Finally, the interface as shown in
Next, we verify the function of D trigger by assignment
4. Functional verification
Signal diagram
The results are shown in
5, Shift register
Shift register can be used to register code, and can also be used to realize serial parallel conversion of data, numerical operation and data processing.
1. Basic concepts
- Shift register (foreign name: shift register) in digital circuit is a trigger based device that works under several same time pulses. Data is input into the device in parallel or serial mode, and then each time pulse moves one bit to the left or right in turn for output at the output end.
- Shift registers can be divided into one-dimensional and multi-dimensional shift registers. The input and output data of the multi-dimensional shift register itself is some column bits.
2. Principle introduction
The schematic diagram of the four bit shift register is shown in the figure. F 0, F 1, F 2 and F 3 are d flip flops triggered by four edges. The output Q of each flip-flop is connected to the input D of the flip-flop on the right. Because there is a delay time from the rising edge of the clock signal CP added to the trigger to the stable establishment of the new state at the output, when the clock signal is added to four triggers at the same time, each trigger receives the original data in the left trigger (input data d 1 received by F 0). The data in the register is shifted one bit to the right in turn.
3. Register classification
- According to the shift direction, it is often divided into left shift register, right shift register and bidirectional shift register.
- According to the input-output mode of shift data, it can be divided into four circuit structures: serial input serial output, serial input parallel output, parallel input serial output and parallel input parallel output.
- In addition, some shift registers also have the function of preset number, which can put data into registers in parallel.
- The shift register can be used for data operation and data processing, realize the serial parallel conversion of data, and can also be connected to various shift register counters, such as ring counter, torsion ring counter, etc.
6, Shift register function verification
1. Verilog implementation shift register
shift_reg.v
module shift_reg (
input clk ,
input rst_n ,
input [3:0] din ,
input dsr ,
input en ,
input [1:0] mode ,
output [3:0] dout ,
output one_out
);
//Signal definition
reg [3:0] dout_r ;
reg one_out_r ;
//output
always @(posedge clk or negedge rst_n) begin
if(~rst_n)begin
dout_r <= 0;
one_out_r <= 0;
end
else if(en)begin
case({mode,dsr})
3'b000:begin
dout_r <= dout_r;
one_out_r <= 0;
end
3'b001:begin
dout_r <= dout_r;
one_out_r <= 0;
end
3'b010:begin
dout_r <= {dsr,dout_r[3:1]};
one_out_r <= dout_r[0];
end
3'b011:begin
dout_r <= {dsr,dout_r[3:1]};
one_out_r <= dout_r[0];
end
3'b100:begin
dout_r <= {dout_r[2:0],dsr};
one_out_r <= dout_r[3];
end
3'b101:begin
dout_r <= {dout_r[2:0],dsr};
one_out_r <= dout_r[3];
end
3'b110:begin
dout_r <= din;
one_out_r <= 0;
end
3'b111:begin
dout_r <= din;
one_out_r <= 0;
end
default:begin
dout_r <= dout_r;
one_out_r <= 0;
end
endcase
end
else begin
dout_r <= 0;
one_out_r <= 0;
end
end
assign dout = dout_r;
assign one_out = one_out_r;
endmodule
shift_reg_top.v
module shift_reg_top (
input clk,
input rst_n,
output [3:0] dout,
output one_out
);
//Signal definition
wire en;
wire [3:0] din;
wire dsr;
wire mode;
//Modular instantiation
shift_reg u_shift_reg
(
.clk (clk),
.rst_n (rst_n),
.din (din),
.dsr (dsr),
.en (en),
.mode (mode),
.dout (dout),
.one_out (one_out)
);
endmodule
Create issp and instantiate endogenous and probes
module shift_reg_top (
input clk,
input rst_n,
output [3:0] dout,
output one_out
);
//Signal definition
wire en;
wire [3:0] din;
wire dsr;
wire mode;
wire [12:0] probe;
//Modular instantiation
shift_reg u_shift_reg
(
.clk (clk),
.rst_n (rst_n),
.din (din),
.dsr (dsr),
.en (en),
.mode (mode),
.dout (dout),
.one_out (one_out)
);
issp u_issp
(
.source({en,din,dsr,mode}),
.probe(probe)
)
endmodule
2. Functional verification
①
②
③
④
