1) Experimental platform: new starting point V2 development board of punctual atom
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2) Full set of experimental source code + manual + video download address: http://www.openedv.com/thread-300792-1-1.html
3) Students interested in punctual atomic FPGA can add group discussion: 994244016
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Chapter 10 key control buzzer experiment

Buzzer is an electronic sounder commonly used in modern times, which is mainly used to generate sound signals. Buzzer has been widely used in daily life. Its typical applications include various alarm devices in medical, fire and other fields, as well as various alarms in daily life. In this chapter, we mainly learn how to use keys to control the buzzer to sound.
This chapter includes the following parts:
1010.1 introduction
10.2 experimental tasks
10.3 hardware design
10.4 program design
10.5 download verification
10.1 introduction
The buzzer is mainly divided into active buzzer and passive buzzer according to the driving mode. The main difference is whether the buzzer contains vibration source. The general active buzzer has its own vibration source, which will sound as long as it is powered on. Since the passive buzzer does not contain an internal oscillation source, it needs an external oscillation signal to sound.

Figure 10.1.1 active buzzer on the left and passive buzzer on the right

Figure 10.1.2 active buzzer used in this experiment
As shown in figure 10.1.1, the two buzzers are very similar in appearance. If the pins of the two buzzers are placed upward, it can be seen that the one with green circuit board is a passive buzzer, and the one without circuit board and closed with black glue is an active buzzer.
Compared with the active buzzer, the passive buzzer has lower cost and controllable sound frequency. The control of the active buzzer is relatively simple. Due to the internal oscillation source, it can sound as long as the appropriate DC voltage is added. The buzzer used in this experiment is the active buzzer in figure 10.1.2.
10.2 experimental tasks
The experimental task in this section is to use the key to control the buzzer to sound. The initial state is buzzer ringing. After pressing the switch, the buzzer stops ringing. Press the switch again, the buzzer will ring again.
10.3 hardware design

Figure 10.3.1 schematic diagram of buzzer control circuit
Figure 10.3.1 is the schematic diagram of the buzzer control circuit. We can see that the buzzer is controlled by a triode. Here, the triode acts as a switch, and its base is connected to the IO pin of the FPGA. When the FPGA output is high, the triode is turned on, the buzzer beeps, otherwise the buzzer stops beeping.
The pin allocation of this experiment is shown in the following table:
Table 10.3.1 pin distribution of key control buzzer test

The corresponding TCL constraint statements are as follows:
set_location_assignment PIN_E16 -to key
set_location_assignment PIN_D12 -to beep
set_location_assignment PIN_M2 -to sys_clk
set_location_assignment PIN_M1 -to sys_rst_n
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to beep
It should be noted that due to the large driving current required by the buzzer, the buzzer may sound less when using the default 8mA driving current. The solution is to modify the driving current output by the buzzer to 12mA or 16mA, as shown in the figure below:

Figure 10.3.2 pin distribution diagram of key control buzzer
Of course, you can also modify it in the corresponding TCL constraint statement, as shown in the last line of TCL above. The specific method you use depends on your preferences.
10.4 program design
According to the experimental task, we only need to change the beeping state of the buzzer when the key is pressed, but in fact, there is the interference of key jitter in the process of key pressing, which is reflected in the changing high and low levels in the digital circuit. In order to avoid collecting the wrong key state in the process of jitter, we need to eliminate the jitter of key data. Therefore, the system shall at least include key anti chattering module and buzzer control module. The block diagram of key control buzzer system is shown in figure 10.4.1.

Figure 10.4.1 system block diagram of key control buzzer
Here we add how to view the module port and signal connection diagram generated by the software. First compile the project, and then click Tools → NetList Viewers → RTL Viewer on the menu bar, as shown in figure 10.4.2:

Figure 10.4.2 port opening and signal connection diagram
You can see the module port and signal connection diagram generated by the software later, as shown in figure 10.4.3:

Figure 10.4.3 port and signal connection diagram
It should be noted that the module port and signal connection diagram can only be opened after synthesis or compilation. After opening, press the [Ctrl] key on the keyboard and scroll the mouse wheel to zoom in and out the generated connection diagram. Module port and signal connection diagram can clearly view the signal connection of each module port. At the same time, double-click the module to further view the schematic diagram of the module.
According to the connection diagram in figure 10.4.3, the top-level module exemplifies the following two modules, key_debounce module and beep_control module. The top_key_beep completes the instantiation of the other two modules. The key jitter elimination module mainly plays the role of delay sampling to prevent the interference of key jitter. The buzzer control module plays the role of controlling the buzzer by identifying the key signal.
key_debounce module: delay sampling the key signal and output the key signal and key data effective signal after debouncing to beep_control module.
beep_control module: controls the beep of the buzzer according to the input key signal and key data effective signal.
Here we introduce the principle of key chattering elimination. Usually, the switch we use is a mechanical elastic switch. When we press or release the key, it cannot be closed or disconnected immediately due to the physical characteristics of the shrapnel. It often produces mechanical jitter within a short time of opening or closing. The process of eliminating this jitter is called key jitter elimination.
Key deblocking can be divided into hardware deblocking and software deblocking. Hardware anti chattering mainly uses RS trigger or capacitor to realize anti chattering, which is generally used when there are few keys. The principle of software anti chattering is mainly to delay sampling for 5ms-20ms after the key is pressed or released, or to sample after detecting that the key state is stable, that is, to avoid the jitter area, as shown in figure 10.4.4.

Figure 10.4.4 schematic diagram of key chattering elimination
The top-level module code is as follows:

1   module top_key_beep(
2       input        sys_clk,       //Clock signal 50Mhz
3       input        sys_rst_n,     //Reset signal
4       
5       input        key,           //Key signal       
6       output       beep           //Buzzer control signal
7       );
8       
9   //wire define
10  wire key_value;
11  wire key_flag;
12  
13  //*****************************************************
14  //**                    main code
15  //*****************************************************
16  
17  //Example key anti shake module
18  key_debounce u_key_debounce(
19      .sys_clk        (sys_clk),
20      .sys_rst_n      (sys_rst_n),
21      
22      .key            (key),
23      .key_flag       (key_flag),
24      .key_value      (key_value)
25      );
26  
27  //Example buzzer control module
28  beep_control u_beep_control(
29      .sys_clk        (sys_clk), 
30      .sys_rst_n      (sys_rst_n),
31      
32      .key_flag       (key_flag),      
33      .key_value      (key_value),
34      .beep           (beep)
35      );
36      
37  endmodule 
In the top-level module, the key anti chattering module and the key control buzzer module are exemplified.
The code of key anti shake module is as follows:
1   module key_debounce(
2       input            sys_clk,          //External 50M clock
3       input            sys_rst_n,        //External reset signal, low effective
4       
5       input            key,              //External key input
6       output reg       key_flag,         //Key data valid signal
7       output reg       key_value         //Data after key debounce  
8       );
9   
10  //reg define    
11  reg [31:0] delay_cnt;
12  reg        key_reg;
13  
14  //*****************************************************
15  //**                    main code
16  //*****************************************************
17  always @(posedge sys_clk or negedge sys_rst_n) begin 
18      if (!sys_rst_n) begin 
19          key_reg   <= 1'b1;
20          delay_cnt <= 32'd0;
21      end
22      else begin
23          key_reg <= key;
24          if(key_reg != key)             //Once a key state change is detected (a key is pressed or released)
25              delay_cnt <= 32'd1000000;  //Reload the initial value for the delay counter (counting time is 20ms)
26          else if(key_reg == key) begin  //When the key state is stable, the counter decreases and starts the 20ms countdown
27                  if(delay_cnt > 32'd0)
28                      delay_cnt <= delay_cnt - 1'b1;
29                  else
30                      delay_cnt <= delay_cnt;
31              end           
32      end   
33  end
34  
35  always @(posedge sys_clk or negedge sys_rst_n) begin 
36      if (!sys_rst_n) begin 
37          key_flag  <= 1'b0;
38          key_value <= 1'b1;          
39      end
40      else begin
41          if(delay_cnt == 32'd1) begin   //When the counter decreases to 1, it indicates that the stable state of the key has been maintained for 20ms
42              key_flag  <= 1'b1;         //At this time, the de dithering process ends and a clock cycle flag signal is given
43              key_value <= key;          //And register the value of the key at this time
44          end
45          else begin
46              key_flag  <= 1'b0;
47              key_value <= key_value; 
48          end  
49      end   
50  end
51      
52  endmodule  

The 25th line of the program continuously detects the key state. Once the key state is found to change, it will be sent to the counter delay_cnt has an initial value of 1000000. When the key state does not change, delay_cnt decrements to realize the countdown function. In the countdown process, once the key state is detected to change, it indicates that there is jitter. At this time, it is given to delay again_ CNT sets the initial value and starts a new round of countdown. Driven by 50Mhz clock, delay_ If CNT can decrease from 1000000 to 1, it means that the key state remains stable for 20ms. At this time, a clock cycle notification signal key is output_ Flag and register and output the key data at this time.
The code of buzzer control module is as follows:

1   module beep_control(
2       //input
3       input        sys_clk,     //System clock
4       input        sys_rst_n,   //Reset signal, active at low level
5       
6       input        key_flag,    //Key valid signal
7       input        key_value, //Key signal after dithering  
8       output  reg  beep         //Buzzer control signal  
9   );
10  
11  //*****************************************************
12  //**                    main code
13  //*****************************************************
14  always @ (posedge sys_clk or negedge sys_rst_n) begin
15      if(!sys_rst_n)
16          beep <= 1'b1;
17      else if(key_flag && (~key_value))  //Judge whether the key is pressed effectively
18          beep <= ~beep;        
19  end
20      
21  endmodule 

The initial state of beep is high level, and the buzzer rings. When the key effective signal key is detected_ Flag is high level, and key signal key_ When value is low, it means that the key is effectively pressed. At this time, beep is reversed and the buzzer stops ringing. When the key is pressed again, beep is reversed again, and the buzzer starts ringing again.
To validate our program, we simulated the code in modelsim.
The Test bench module code is as follows

1   `timescale 1 ns/ 1 ns
2   module tb_top_key_beep();
3   
4   //parameter define
5   parameter T = 20;
6   
7   //reg define
8   reg  key;
9   reg  sys_clk;
10  reg  sys_rst_n;
11  reg  key_value;
12  
13  // wire define                                               
14  wire beep;
15  
16  //*****************************************************
17  //**                    main code                  
18  //*****************************************************
19  
20  //Give signal initial value
21  initial begin
22      key                          <= 1'b1;
23      sys_clk                      <= 1'b0;
24      sys_rst_n                    <= 1'b0; 
25      #20           sys_ rst_ n      <= 1'b1;  // At the 20th ns, the reset signal is pulled high 
26      #30           key            <= 1'b0;  // Press the key at 50ns
27      #20           key            <= 1'b1;  // Analog jitter
28      #20           key            <= 1'b0;  // Analog jitter
29      #20           key            <= 1'b1;  // Analog jitter
30      #20           key            <= 1'b0;  // Analog jitter
31      #170          key            <= 1'b1;  // Release the key at 300ns
32      #20           key            <= 1'b0;  // Analog jitter
33      #20           key            <= 1'b1;  // Analog jitter
34      #20           key            <= 1'b0;  // Analog jitter
35      #20           key            <= 1'b1;  // Analog jitter
36      #170          key            <= 1'b0;  // Press the key again at 550ns
37      #20           key            <= 1'b1;  // Analog jitter
38      #20           key            <= 1'b0;  // Analog jitter
39      #20           key            <= 1'b1;  // Analog jitter
40      #20           key            <= 1'b0;  // Analog jitter
41      #170          key            <= 1'b1;  // Release the key at 800ns
42      #20           key            <= 1'b0;  // Analog jitter
43      #20           key            <= 1'b1;  // Analog jitter
44      #20           key            <= 1'b0;  // Analog jitter
45      #20           key            <= 1'b1;  // Analog jitter
46  end
47  
48  //For a 50Mhz clock, the cycle is 1/50Mhz=20ns, so the level is reversed every 10ns  
49  always # (T/2) sys_clk <= ~sys_clk;
50  
51  //Instantiate key_beep module                        
52  top_key_beep u1 (
53      .beep(beep),
54      .key(key),
55      .sys_clk(sys_clk),
56      .sys_rst_n(sys_rst_n)
57  );           
58                                      
59  endmodule

The simulation waveform is as follows:

Figure 10.4.5 simulation waveform
In the test code, in order to facilitate the viewing of the simulation waveform, the delay time of delay sampling in the key anti shake module is changed to four clock cycles (the code in line 26 of the key anti shake module is delay_cnt < = 32'd1000000; it is changed to delay_cnt < = 32'd4;). tb_ key_ The 22nd to 45th lines in the beep module are excited by the signal. It can be seen from figure 10.4.5 that at 50ns, the key is pulled down, and the key jitter is simulated at 50 to 130ns. It can be seen that the key is turned off at the 4th clock cycle after the key jitter stops_ The flag shows a high level of a clock cycle, and beep is pulled low (the buzzer stops ringing); Release the key at 300ns, and then simulate the key jitter. Similarly, it can be seen that the fourth clock cycle after the jitter is over, key_ The flag signal is pulled high. Readers can carefully observe the simulation waveform, deeply understand the code and carefully experience the key_ The relationship between flag signal and key signal.
10.5 download verification
First, we open the key control buzzer project and open top under the path where the project is located_ key_ In the beep / par folder, find "top_key_beep.qpf" and double-click to open it. Note that the path name of the project can only be composed of letters, numbers and underscores, and Chinese, spaces and special characters are not allowed. top_ key_ After the beep project is opened, it is shown in figure 10.5.1.

Figure 10.5.1 opening project
After the project is opened, click the "Programmer" icon in the toolbar (the red box in the figure) to open the download interface.
The download interface is shown in figure 10.5.2 (the download has been completed in the figure). Check whether the downloaded file (sof file) has been loaded in the figure. If not, click the "Add File" button to add the key in the water lamp project_ led/par/output_ The "key_led.sof" file in the files directory.

Figure 10.5.2 Download Interface

Figure 10.5.3 new starting point buzzer
After the development board is powered on, click "Hardware Setup" in the program download interface, and select the current hardware connection as "USB blaster" in the pop-up dialog box. Then click "Start" to download the sof file obtained after the project compilation to the development board.
After downloading, you can use the key to control the buzzer.