STM32 ~ configure the clock frequency [this article takes you to solve the STM32 main frequency configuration], with answers + test points

  users can configure the frequencies of AHB bus, high-speed APB2 bus and low-speed APB1 bus through multiple prescalers. The maximum frequency of the AHB and APB2 domains is 72 MHz. The maximum allowable frequency of APB1 domain is 36 MHz. The clock frequency of SDIO interface is fixed as HCLK/2.

The 40 kHz LSI is used by the independent watchdog IWDG. In addition, it can also be selected as the clock source of the Real-Time Clock RTC. In addition, the clock source of Real-Time Clock RTC can also select LSE or 128 frequency division of HSE. The clock source of RTC is selected through RTCSEL[1:0].

STM32 has a full speed USB module, and its serial interface engine needs a clock source with a frequency of 48MHz. The clock source can only be obtained from the PLL output, and can be selected as 1.5 frequency division or 1 frequency division. That is, when the USB module needs to be used, the PLL must be enabled, and the clock frequency is configured as 48MHz or 72MHz.

In addition, STM32 can also select a PLL output frequency division 2, HSI, HSE, or system clock SYSCLK to output to MCO pin (PA8). The system clock SYSCLK is the clock source for most parts of STM32. It can be PLL output, HSI or HSE (PLL frequency doubling to 72Mhz is used in general procedures). Before selecting the clock source, pay attention to judge whether the target clock source has oscillated stably. Max=72MHz, which is divided into two channels. One channel is sent to i2s2clk and i2s3clk used by I2S2 and I2S3; Another channel is divided by AHB frequency divider (1 / 2 / 4 / 8 / 16 / 64 / 128 / 256 / 512) and sent to the following 8 modules for use:

  1. Send SDIOCLK clock used by SDIO.

  2. Send FSMCCLK clock used by FSMC.

  3. HCLK clock for AHB bus, kernel, memory and DMA.

  4. The system timer clock (SysTick) sent to Cortex after 8 frequency division.

  5. The idle running clock FCLK directly sent to Cortex.

  6. To APB1 divider. APB1 frequency divider can select 1, 2, 4, 8 and 16 frequency divisions. One of its outputs is used by APB1 peripherals (PCLK1, maximum frequency 36MHz), and the other is sent to timer (Timer2-7)2, 3 and 4 frequency multipliers. The frequency multiplier can select 1 or 2 frequency multipliers, and the clock output is used by timers 2, 3, 4, 5, 6 and 7.

  7. Send it to APB2 frequency divider. APB2 frequency divider can select 1, 2, 4, 8 and 16 frequency divisions. One of its outputs is for APB2 peripherals (PCLK2, maximum frequency 72MHz), and the other is for timers (Timer1 and Timer8)1 and 2 frequency multipliers. The frequency multiplier can select 1 or 2 frequency multipliers, and the clock output is used by timer 1 and timer 8. In addition, APB2 frequency divider has another output for ADC frequency divider. After frequency division, ADCCLK clock is obtained and sent to ADC module for use. ADC frequency divider can be selected as 2, 4, 6 and 8 frequency division.

  8. 2 after frequency division, it is sent to SDIO AHB interface for use (HCLK/2).

Detailed reference:

2. External crystal oscillator as clock source

Next, solve how to configure the 12M external crystal oscillator as the system clock source.

The first step is to modify the HSE in stm32f10x.h_ Value is 12000000

/**

 * @brief In the following line adjust the value of External High Speed oscillator (HSE)

   used in your application 

   

   Tip: To avoid modifying this file each time you need to use different HSE, you

        can define the HSE value in your toolchain compiler preprocessor.

  */           

#if !defined  HSE_VALUE

 #ifdef STM32F10X_CL   

  #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */

 #else 

  #define HSE_VALUE    ((uint32_t)12000000) /*!< Value of the External oscillator in Hz */

 #endif /* STM32F10X_CL */

#endif /* HSE_VALUE */



Step 2: modify the system_ For the clock configuration in stm32f10x. C, first find void SystemInit(void) - "SetSysClock()" SetSysClockTo72(), and change the 9-octave frequency to 6-octave frequency, 12*6=72MHz

/**

  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 

  *         and PCLK1 prescalers. 

  * @note   This function should be used only after reset.

  * @param  None

  * @retval None

  */

static void SetSysClockTo72(void)

{

  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;

  

  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    

  /* Enable HSE */    

  RCC->CR |= ((uint32_t)RCC_CR_HSEON);

 

  /* Wait till HSE is ready and if Time out is reached exit */

  do

  {

    HSEStatus = RCC->CR & RCC_CR_HSERDY;

    StartUpCounter++;  

  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));



  if ((RCC->CR & RCC_CR_HSERDY) != RESET)

  {

    HSEStatus = (uint32_t)0x01;

  }

  else

  {

    HSEStatus = (uint32_t)0x00;

  }  



  if (HSEStatus == (uint32_t)0x01)

  {

    /* Enable Prefetch Buffer */

    FLASH->ACR |= FLASH_ACR_PRFTBE;



    /* Flash 2 wait state */

    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);

    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    



 

    /* HCLK = SYSCLK */

    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;

      

    /* PCLK2 = HCLK */

    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;

    

    /* PCLK1 = HCLK */

    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;



#ifdef STM32F10X_CL

    // ...

#else    

    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */

    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |

                                        RCC_CFGR_PLLMULL));

    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); // 12

#endif /* STM32F10X_CL */



    /* Enable PLL */

    RCC->CR |= RCC_CR_PLLON;



    /* Wait till PLL is ready */

    while((RCC->CR & RCC_CR_PLLRDY) == 0)

    {


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Tags: Android Design Pattern stm32

Posted on Tue, 23 Nov 2021 21:50:04 -0500 by hawk72500