makeFile learning diary II (C + +) variables, automatic derivation, style and clearing in makeFile

edit : main.o kbd.o command.o dislplay,o \
insert.o search.o files.o utils.o 
cc -o edit main.o kbd.o command.o dislplay,o \
insert.o search.o files.o utils.o 

main.o : main.c defs.h
cc -c main.c
kbd.o : kbd.c defs.h command.h
cc -c kbd.c
command.o :command.c defs.h command.h 
cc -c insert.c 
display.o :display.c defs.h buffer.h 
cc -c display.c 
insert.o :insert.c defs.h buffer.h 
cc -c insert.c 
search.o :search.c defs.h buffer.h 
cc -c search.c 
files.o :files.c defs.h buffer.h command.h
cc -c files.c 
utils.o :utils.c defs.h buffer.h 
cc -c utils.c 

clean:
rm edit main.o kbd.o command.o display.o \
insert.o search.o files.o utils.o

The above is the code example cited in my last article. Now let's explain it with this example.

1, Variables in Makefile

edit : main.o kbd.o command.o dislplay,o insert.o search.o files.o utils.o 
cc -o edit main.o kbd.o command.o dislplay,o insert.o search.o files.o utils.o 

First, explain the rules of edit:

        (. o) the library file has been written twice here. Of course, if it is completely written, it needs to be written again in clean. When a new (. o) file is introduced into our project, we need to add them in these two places, but as the complexity of the code increases, the work may become cumbersome and we may forget it. Therefore, the variable (string) in Make file is introduced, which can be understood as a macro in C language.

For example, we can declare an objects variable or OBJ, and we can define it at the beginning of the Make file file:

objects = main.o kbd.o command.o \
insert.o search.o files.o utils.o

Then we can use this variable with "$(objects)" in the makefile. Here is what it looks like after the revision

objects = main.o kbd.o command.o \
insert.o search.o files.o utils.o

edit : $(objects)
cc -o edit $(objects)

main.o : main.c defs.h
cc -c main.c
kbd.o : kbd.c defs.h
cc -c kbd.c
command.o :command.c defs.h command.h 
cc -c insert.c 
display.o :display.c defs.h buffer.h 
cc -c display.c 
insert.o :insert.c defs.h buffer.h 
cc -c insert.c 
search.o :search.c defs.h buffer.h 
cc -c search.c 
files.o :files.c defs.h buffer.h command.h
cc -c files.c 
utils.o :utils.c defs.h buffer.h 
cc -c utils.c 

clean:
rm edit $(objects)

In this way, when we add a new storage file, we only need to add it in the variable.

2, Automatic derivation of Make

         GUN's make function is very powerful. It can automatically deduce the file and the commands after the file, so we don't need to write the same command after every (, o) file. It can automatically push to the command.

        How to operate? When make finds a (. O) file, it will automatically add the (, c) file to the dependency. For example, if make finds a file of a.o, the a.c file is the dependent file of a.o, and CC - C, a and C will be automatically completed by him. Therefore, we can also omit the above code:

objects = main.o kbd.o command.o \
insert.o search.o files.o utils.o

edit : $(objects)
cc -o edit $(objects)

main.o : defs.h
kbd.o : defs.h command.h
command.o : defs.h command.h 
display.o : defs.h buffer.h 
insert.o : defs.h buffer.h 
search.o : defs.h buffer.h 
files.o : defs.h buffer.h command.h
utils.o : defs.h buffer.h 

.PHONY:clean
clean:
rm edit $(objects)

The (. PHONY) above indicates that clean is a pseudo target file. We'll talk about this later.

3, Makefile style

There is also a more simple style, but it is not so easy to understand. I post it and you can understand it yourself

objects = main.o kbd.o command.o \
insert.o search.o files.o utils.o

edit : $(objects)
cc -o edit $(objects)

$(objects) :defs.h
kbd.o command.o files.o : command.h
display.o insert.o search.o files.o :buffer.h

.PHONY:clean
clean:
rm edit $(objects)

Hey! It's not suitable for a stupid person like me to write such a book. It takes a lot of brains.

4, Rules for emptying target files

Every makefile file should write a rule to empty the target file, which can ensure the cleanliness of our files,

There are two ways to write it

Writing method 1:

clean:
rm edit $(objects)

Method 2:

.PHONY:clean
clean:
-rm edit $(objects)

In fact, the second way of writing is a more stable way of writing.

         (. PHONY) mentioned earlier that he would mark clean as a pseudo target.

         What's the use of adding a "-" before rm? It will ignore some problems in rm files and continue to perform the following things,

As for why, clean is placed at the end of the file. In fact, it can be placed anywhere. We are used to it.

Tags: Makefile Back-end

Posted on Mon, 06 Dec 2021 15:12:21 -0500 by breath18