ALINX video learning notes vivado initial experience led project

//Xiaobai entry record, when the e-notebook is used, the learning video comes from the official ALINX of station b. The board I use is ALINX zynq7020 purchased, so follow this tutorial.

[ALINX] FPGA ZYNQ video tutorial - AX7010/AX7020 tutorial - FPGA experiment_ Beep beep beep_ bilibili

led.v file code with comments

module led(
    input sys_clk,
    input rst_n,
    (* MARK_DEBUG="true" *)output reg [3:0] led
(* MARK_DEBUG="true" *)reg[31:0] timer_cnt;
always@(posedge sys_clk or negedge rst_n)
    if (!rst_n)
        led <= 4'd0 ;
        timer_cnt <= 32'd0 ;
    else if(timer_cnt >= 32'd49_999_999)
        led <= ~led;
        timer_cnt <= 32'd0;
        led <= led;
        timer_cnt <= timer_cnt + 32'd1;

Instantiate ila in source file
//ila ila_inst(
//  .clk(sys_clk),
//  .probe0(timer_cnt),
//  .probe1(led)
//  );


Code snippet of led.xdc constraint file automatically generated after constraint pin and clock constraints. 1. The constraint pin is opened through the "window I / O ports" in the toolbar, and the pin and voltage value are automatically generated according to the user manual. 2. The clock constraint is opened through the "comprehensive open synthesized design constraints Wizard" on the left. Select the clock 50MHz and generate it automatically.

set_property PACKAGE_PIN M14 [get_ports {led[0]}]
set_property PACKAGE_PIN M15 [get_ports {led[1]}]
set_property PACKAGE_PIN K16 [get_ports {led[2]}]
set_property PACKAGE_PIN J16 [get_ports {led[3]}]
set_property PACKAGE_PIN N15 [get_ports rst_n]
set_property PACKAGE_PIN U18 [get_ports sys_clk]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports rst_n]
set_property IOSTANDARD LVCMOS33 [get_ports sys_clk]

create_clock -period 20.000 -name sys_clk -waveform {0.000 10.000} [get_ports sys_clk]

After generating the bitstream, you can download the bitstream to the board through open hardware manager. Let's talk about simulation.

Right click simulation simulation settings to set simulation settings.

For simulation, you need to add the simulation incentive file, "add sources add or create simulation sources", create the file "vtf_led_test.v", and copy the routine code as follows.

`timescale 1ns / 1ps
// Module Name: vtf_led_test

module vtf_led_test;
// Inputs
reg sys_clk;
reg rst_n ;
// Outputs
wire [3:0] led;

// Instantiate the Unit Under Test (UUT)
led uut (

// Initialize Inputs
    sys_clk = 0;
    rst_n = 0 ;
    #1000 ;
    rst_n = 1; 
//Create clock
always #10 sys_clk = ~ sys_clk;  


The following are some basic operations, run behavior level simulation,

  During simulation, the signal can be set to display what we want (for example, the counter displays decimal digits instead of hexadecimal). Right click the signal, and select fixed or unsigned decimal directly.

After simulating 1s, it can be seen that the counter reaches 4999 when it is 1s_ 9999, led is on (F).

  The simulation file will occupy the resources of the sim folder in the directory. The simulation time will be very long, and the useless simulation can be deleted. The large file is under this path.

  In the tutorial, you will power on and operate the board later

Later, we will talk about the use of the embedded logic analyzer, which is to export the actual waveform diagram inside the board through IP "ila".

If you use ila later, record it in detail. This is the end of learning.

Posted on Fri, 29 Oct 2021 23:42:28 -0400 by cyber_ghost