Embedded Linux--V3s--SPITFT -- no CS pin

Dilemma: the screen has no CS pin

If there is cs pin: st7789v device tree description

&spi0{
		status = "okay";
		st7789v: st7789v@0{
			compatible = "sitronix,st7789v";
			reg = <0>;
			status = "okay";
			spi-max-frequency = <36000000>;
			spi-cpol;
			spi-cpha;
			rotate = <0>;
			fps = <60>;
			buswidth = <8>;
			
			dc-gpios    = <&pio 1 4 GPIO_ACTIVE_HIGH>;  // PB4 
			reset-gpios = <&pio 1 5 GPIO_ACTIVE_HIGH>;  // PB5
			//led-gpios   = <&pio 1 7 GPIO_ACTIVE_LOW>; // PB7
			width = <240>;
			height= <320>;
			debug = <0>;
		};
}

It can be displayed normally.

If there is no CS pin:

I don't know how to write a device tree.

Learn the description of Quanzhi's spi bus

  • SPI cpol - (optional) the null attribute specifies that the device requires reverse clock polarity (CPOL) mode.
  • SPI CPHA - (optional) the null attribute specifies the shift clock phase (CPHA) mode required by the device.
  • SPI CS high - (optional) the empty attribute specifies the device needs, and the chip selection high level is valid
  • spi-3wire - (optional) the empty attribute specifies that the device requires 3-wire mode.
  • SPI LSB first - (optional) the empty attribute specifies the LSB priority mode required by the device.
  • SPI TX bus width - (optional) bus width (number of data lines) for MOSI. If it does not exist, it defaults to 1.
  • SPI RX bus width - (optional) bus width (number of data lines) for MISO. If it does not exist, it defaults to 1.
  • SPI RX delay us - (optional) read the microsecond delay after transmission.
  • SPI TX delay us - (optional) microsecond delay after write transfer.
  • SPI bits per word - (optional) the word size of the data transfer. If it does not exist, the default value is 8.

reference resources: https://www.136.la/jingpin/show-164614.html

Working mode 1:
  when CPHA=0 and CPOL=0, SPI bus works in mode 1. The data on the MISO pin has been online before the first SPSCK edge jumps. In order to ensure correct transmission, the MSB bit of the MOSI pin must be synchronized with the first edge of the SPSCK. In the SPI transmission process, first put the data online, and then when synchronizing the rising edge of the clock signal, the receiver of the SPI captures the bit signal. At the end of a cycle (falling edge) of the clock signal, The next bit data signal goes online, and then repeat the above process until the transmission of 8-bit signal of one byte is completed.

Working mode 2:
  when CPHA=0 and CPOL=1, SPI bus works in mode 2. The only difference from the former is that the bit signal is captured at the falling edge of the synchronous clock signal, and the next bit data is on the line at the rising edge.

Working mode 3:
  when CPHA=1 and CPOL=0, SPI bus works in mode 3. The MSB bit of data on MISO pin and MOSI pin must be synchronized with the first edge of SPSCK. During SPI transmission, the data is online at the beginning of the synchronization clock signal cycle (rising edge), and then the receiver of SPI captures the bit signal at the falling edge of the synchronization clock signal. At the end of a cycle of the clock signal (rising edge), the next bit data signal is online, Repeat the above process until the 8-bit signal transmission of one byte is completed.

Working mode 4:
  when CPHA=1 and CPOL=1, SPI bus works in mode 4. The only difference from the former is that the bit signal is captured at the rising edge of the synchronous clock signal, and the next bit data is on the line at the falling edge.

#define SPI_CPHA      0x01 /* clock phase */
#define SPI_CPOL      0x02 /* clock polarity */
#define SPI_MODE_0   (0|0) /* (original MicroWire) */
#define SPI_MODE_1   (0|SPI_CPHA)
#define SPI_MODE_2   (SPI_CPOL|0)
#define SPI_MODE_3   (SPI_CPOL|SPI_CPHA)
#define SPI_CS_HIGH   0x04 /* chipselect active high? */
#define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */
#define SPI_3WIRE     0x10 /* SI/SO signals shared */
#define SPI_LOOP      0x20 /* loopback mode */
#define SPI_NO_CS     0x40 /* 1 dev/bus, no chipselect */
#define SPI_READY     0x80 /* slave pulls low to pause */
#define SPI_ CPHA 0x01 / / clock phase 
#define SPI_ Cpol 0x02 / / clock phase
#define SPI_ MODE_ 0 (0 × 0) / / mode 0 
#define SPI_MODE_1     (0|SPI_CPHA) / / mode 1 
#define SPI_ MODE_ 2     (SPI_ Cpol (0) / / mode 2 
#define SPI_MODE_3     (SPI_CPOL|SPI_CPHA) / / mode 3 
#define SPI_ CS_ High 0x04 / / chip selection high level 
#define SPI_LSB_FIRST   0x08            //LSB 
#define SPI_ 3wire 0x10 / / 3-wire mode SI and SO are the same wire 
#define SPI_ Loop 0x20 / / loopback mode 
#define SPI_ NO_ CS 0x40 / / a single device occupies one SPI bus, so there is no chip selection 
#define SPI_ Ready 0x80 / / pull slave low level to stop data transmission

Tags: Linux stm32

Posted on Sun, 05 Sep 2021 21:58:58 -0400 by alexander.s