ODDR of FPGA Xilinx primitive call

Record background: Recently, you need to call the ODDR primitive because you want to implement GMI to rgmii.

ODDR: Dedicated Dual Data Rate (DDR) Output Register

Through ODDR, the two channels of single end data are combined into one channel for output, the upper and lower edges output data at the same time, and the upper edge outputs a channel and the lower edge outputs b channel; if the two channels of input signals are 1 and 0, the output signal is actually the input clock signal.

The Verilog statement called is:

 1 // ODDR: Output Double Data Rate Output Register with Set, Reset
 2 //       and Clock Enable.
 3 //       7 Series
 4 // Xilinx HDL Language Template, version 2017.4
 6 ODDR #(
 8    .INIT(1'b0),    // Initial value of Q: 1'b0 or 1'b1
 9    .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
10 ) ODDR_inst (
11    .Q(Q),   // 1-bit DDR output
12    .C(C),   // 1-bit clock input
13    .CE(CE), // 1-bit clock enable input
14    .D1(D1), // 1-bit data input (positive edge)
15    .D2(D2), // 1-bit data input (negative edge)
16    .R(R),   // 1-bit reset
17    .S(S)    // 1-bit set
18 );
20 // End of ODDR_inst instantiation

Mode interpretation:

Option? Edge mode:

In this mode, the clock edge is used to capture data from FPGA logic at twice the throughput. This structure is similar to the implementation of virtex-6. Both outputs provide data input or three state control input to IOB.

Save? Edge mode:

In this mode, the data can be sent to the IOB at the same clock edge. Using the same clock edge to send data to IOB can avoid setting up time violation and allow users to use the smallest register to perform higher DDR frequency for register delay instead of using CLB register.




Be careful:

1. Set and reset cannot be set at the same time;

2. The reset of the ODDR primitive requires about 12 clock s. The first input data may have problems (pro test), [because of the company's network, it is unable to upload pictures], but the pro test is so.

Before modifying the code:

wire oddr_do_test;

oddr_test oddr_test


Add the following code:

wire oddr_do_test;

reg [5:0]tx_en_d;
reg [5:0]tx_er_d;
always @ (posedge tx_clk)
    tx_en_d <= {tx_en_d[4:0],tx_en};
    tx_er_d <= {tx_er_d[4:0],tx_er};

oddr_test oddr_test

Tags: Verilog network

Posted on Fri, 03 Apr 2020 18:05:44 -0400 by Secondlaw