FPGA Foundation (verilog language) - syntax

Introduction to verilog

verilog is a language with syntax similar to c, but it is different from c, for example:

1.verilog language is parallel, each always block is executed at the same time, while c language is executed in sequence

2.verilog is also called hardware description language. When programming with verilog, it is better to describe a circuit with verilog, while c is a program

verilog basic syntax

This block only talks about the basic grammar in common use. As for some advanced grammar, we will talk about it later in the case

verilog file. v basic structure


module a(b, c, d,...z);//Module: module header a: module name (b,c,d,...z): port list
    input b;//Input declaration
    input wire c;//Enter and declare wire for wire network type, wire can be omitted
    input wire [7:0] d;//[7:0]: input bus bit width 0 ~ 7, so it is 8 bit bus
    output e;//Output declaration
    output [7:0] f;//Description of the output bus bit width, the default is wire type, wire is omitted here
    output reg [7:0] f;//reg for output bus register type
   ...//In order to reduce the space, e~y declaration should not be omitted in actual code
assign d = a & b;//The assignment statement is also called the data flow modeling statement or the continuous assignment statement, followed by the combination logic assign e = (f < g)? 1 : 0;//ternary operator always @ (posedge a or negedge b or posedge c...)//always statement, posedge is triggered by rising edge, nagedge is triggered by falling edge, followed by a signal that when the signal rises or falls, the following program is executed begin //begin...end is equivalent to () if(!b)//if statement begin h <= 4'b0000;//The nonblocking assignment statement uses < =, 4'b0000 to indicate that the bit width is 4, and the binary number 0000 i <= 32'haabbccdd;//Here is the 32-bit width, and the hexadecimal number aabbccdd end else//else for branch case(j)//case statement 0 : k <= k + 1'b1;//There is no self adding representation in verilog, so k = k + 1'b1 1 : if(k<m) begin l <= 8'd7;j <= 2; end// J < = 2 indicates that the next clock jumps to 2: statement after triggering 2 : m < = 4'b0001 << 2;//< shift symbol default: j <=0; //The default statement means to go when the value of j is not 0,1,2 listed above endcase //case multi branch statement end flag end//End of the entire always loop flag endmodule//End of whole module


That's all. I'll give you more specific examples in the future

Tags: Verilog Programming network C

Posted on Sun, 24 Nov 2019 13:49:38 -0500 by andygrant