Xilinx PCIe IP core example engineering code analysis and simulation

2.1 code analysis

Review the structure of the sample program again:

First open the PCI file in testbench_ exp_ usrapp_ Tx.v, the hierarchical path is board/RP/tx_usrapp, focusing on an initial block:

• Line 308: the name of the test task is specified here as pio_writeReadBack_test0.
• Line 324: here by calling TSK_USR_DATA_SETUP_SEQ task pair DATA_STORE to initialize.
• Line 332: here, the specific content about the test task is added through the file include command ` ` include "tests.vh". Note that the file contents of verilog are different from those of c. verilog directly moves the contents of tests.vh. When you open tests.vh, you can see that there is only one code: \ include "sample_tests1.vh", sample_tests1.vh is the specific content of each test task:

Among them, it is called PIO_ writeReadBack_ The test tasks of Test0 are as follows:

else if(testname == "pio_writeReadBack_test0") begin // This test performs a 32 bit write to a 32 bit Memory space and performs a read back board.RP.tx_usrapp.TSK_SIMULATION_TIMEOUT(10050); board.RP.tx_usrapp.TSK_SYSTEM_INITIALIZATION; board.RP.tx_usrapp.TSK_BAR_INIT; //-------------------------------------------------------------------------- // Event : Testing BARs //-------------------------------------------------------------------------- for (board.RP.tx_usrapp.ii = 0; board.RP.tx_usrapp.ii <= 6; board.RP.tx_usrapp.ii = board.RP.tx_usrapp.ii + 1) begin if (board.RP.tx_usrapp.BAR_INIT_P_BAR_ENABLED[board.RP.tx_usrapp.ii] > 2'b00) // bar is enabled case(board.RP.tx_usrapp.BAR_INIT_P_BAR_ENABLED[board.RP.tx_usrapp.ii]) 2'b01 : // IO SPACE begin $display("[%t] : Transmitting TLPs to IO Space BAR %x", $realtime, board.RP.tx_usrapp.ii); //-------------------------------------------------------------------------- // Event : IO Write bit TLP //-------------------------------------------------------------------------- board.RP.tx_usrapp.TSK_TX_IO_WRITE(board.RP.tx_usrapp.DEFAULT_TAG, board.RP.tx_usrapp.BAR_INIT_P_BAR[board.RP.tx_usrapp.ii][31:0], 4'hF, 32'hdead_beef); board.RP.com_usrapp.TSK_EXPECT_CPL(3'h0, 1'b0, 1'b0, 2'b0, board.RP.tx_usrapp.COMPLETER_ID_CFG, 3'h0, 1'b0, 12'h4, board.RP.tx_usrapp.COMPLETER_ID_CFG, board.RP.tx_usrapp.DEFAULT_TAG, board.RP.tx_usrapp.BAR_INIT_P_BAR[board.RP.tx_usrapp.ii][31:0], test_vars[0]); board.RP.tx_usrapp.TSK_TX_CLK_EAT(10); board.RP.tx_usrapp.DEFAULT_TAG = board.RP.tx_usrapp.DEFAULT_TAG + 1; //-------------------------------------------------------------------------- // Event : IO Read bit TLP //-------------------------------------------------------------------------- // make sure P_READ_DATA has known initial value board.RP.tx_usrapp.P_READ_DATA = 32'hffff_ffff; fork board.RP.tx_usrapp.TSK_TX_IO_READ(board.RP.tx_usrapp.DEFAULT_TAG, board.RP.tx_usrapp.BAR_INIT_P_BAR[board.RP.tx_usrapp.ii][31:0], 4'hF); board.RP.tx_usrapp.TSK_WAIT_FOR_READ_DATA; join if (board.RP.tx_usrapp.P_READ_DATA != 32'hdead_beef) begin $display("[%t] : Test FAILED --- Data Error Mismatch, Write Data %x != Read Data %x", $realtime, 32'hdead_beef, board.RP.tx_usrapp.P_READ_DATA); test_failed_flag = 1; end else begin $display("[%t] : Test PASSED --- Write Data: %x successfully received", $realtime, board.RP.tx_usrapp.P_READ_DATA); end board.RP.tx_usrapp.TSK_TX_CLK_EAT(10); board.RP.tx_usrapp.DEFAULT_TAG = board.RP.tx_usrapp.DEFAULT_TAG + 1; end 2'b10 : // MEM 32 SPACE begin $display("[%t] : Transmitting TLPs to Memory 32 Space BAR %x", $realtime, board.RP.tx_usrapp.ii); //-------------------------------------------------------------------------- // Event : Memory Write 32 bit TLP //-------------------------------------------------------------------------- board.RP.tx_usrapp.DATA_STORE[0] = 8'h04; board.RP.tx_usrapp.DATA_STORE[1] = 8'h03; board.RP.tx_usrapp.DATA_STORE[2] = 8'h02; board.RP.tx_usrapp.DATA_STORE[3] = 8'h01; board.RP.tx_usrapp.TSK_TX_MEMORY_WRITE_32(board.RP.tx_usrapp.DEFAULT_TAG, board.RP.tx_usrapp.DEFAULT_TC, 10'd1, board.RP.tx_usrapp.BAR_INIT_P_BAR[board.RP.tx_usrapp.ii][31:0]+8'h10, 4'h0, 4'hF, 1'b0); board.RP.tx_usrapp.TSK_TX_CLK_EAT(10); board.RP.tx_usrapp.DEFAULT_TAG = board.RP.tx_usrapp.DEFAULT_TAG + 1; //-------------------------------------------------------------------------- // Event : Memory Read 32 bit TLP //-------------------------------------------------------------------------- // make sure P_READ_DATA has known initial value board.RP.tx_usrapp.P_READ_DATA = 32'hffff_ffff; fork board.RP.tx_usrapp.TSK_TX_MEMORY_READ_32(board.RP.tx_usrapp.DEFAULT_TAG, board.RP.tx_usrapp.DEFAULT_TC, 10'd1, board.RP.tx_usrapp.BAR_INIT_P_BAR[board.RP.tx_usrapp.ii][31:0]+8'h10, 4'h0, 4'hF); board.RP.tx_usrapp.TSK_WAIT_FOR_READ_DATA; join if (board.RP.tx_usrapp.P_READ_DATA != ) begin $display("[%t] : Test FAILED --- Data Error Mismatch, Write Data %x != Read Data %x", $realtime, , board.RP.tx_usrapp.P_READ_DATA); test_failed_flag = 1; end else begin $display("[%t] : Test PASSED --- Write Data: %x successfully received", $realtime, board.RP.tx_usrapp.P_READ_DATA); end board.RP.tx_usrapp.TSK_TX_CLK_EAT(10); board.RP.tx_usrapp.DEFAULT_TAG = board.RP.tx_usrapp.DEFAULT_TAG + 1; end 2'b11 : // MEM 64 SPACE begin $display("[%t] : Transmitting TLPs to Memory 64 Space BAR %x", $realtime, board.RP.tx_usrapp.ii); //-------------------------------------------------------------------------- // Event : Memory Write 64 bit TLP //-------------------------------------------------------------------------- board.RP.tx_usrapp.DATA_STORE[0] = 8'h64; board.RP.tx_usrapp.DATA_STORE[1] = 8'h63; board.RP.tx_usrapp.DATA_STORE[2] = 8'h62; board.RP.tx_usrapp.DATA_STORE[3] = 8'h61; board.RP.tx_usrapp.TSK_TX_MEMORY_WRITE_64(board.RP.tx_usrapp.DEFAULT_TAG, board.RP.tx_usrapp.DEFAULT_TC, 10'd1, , 4'h0, 4'hF, 1'b0); board.RP.tx_usrapp.TSK_TX_CLK_EAT(10); board.RP.tx_usrapp.DEFAULT_TAG = board.RP.tx_usrapp.DEFAULT_TAG + 1; //-------------------------------------------------------------------------- // Event : Memory Read 64 bit TLP //-------------------------------------------------------------------------- // make sure P_READ_DATA has known initial value board.RP.tx_usrapp.P_READ_DATA = 32'hffff_ffff; fork board.RP.tx_usrapp.TSK_TX_MEMORY_READ_64(board.RP.tx_usrapp.DEFAULT_TAG, board.RP.tx_usrapp.DEFAULT_TC, 10'd1, , 4'h0, 4'hF); board.RP.tx_usrapp.TSK_WAIT_FOR_READ_DATA; join if (board.RP.tx_usrapp.P_READ_DATA != ) begin $display("[%t] : Test FAILED --- Data Error Mismatch, Write Data %x != Read Data %x", $realtime, , board.RP.tx_usrapp.P_READ_DATA); test_failed_flag = 1; end else begin $display("[%t] : Test PASSED --- Write Data: %x successfully received", $realtime, board.RP.tx_usrapp.P_READ_DATA); end board.RP.tx_usrapp.TSK_TX_CLK_EAT(10); board.RP.tx_usrapp.DEFAULT_TAG = board.RP.tx_usrapp.DEFAULT_TAG + 1; end default : $display("Error case in usrapp_tx\n"); endcase end $display("[%t] : Finished transmission of PCI-Express TLPs", $realtime); if (!test_failed_flag) begin $display ("Test Completed Successfully"); end $finish; end

You can see that the task function is: this test performs 32-bit write operations to 32-bit memory space and performs read back operations.

• The first task is board.RP.tx_usrapp.TSK_SIMULATION_TIMEOUT(10050);, The purpose of this task is to set the RX of the simulation_ The value of timeout in usrapp. We can use pci_exp_usrapp_rx.v, this value is used to report an error and end the simulation if the link has not been established.
• TSK_SYSTEM_INITIALIZATION task: this task is used to wait for the completion of Transaction reset and link establishment.
• TSK_BAR_INIT: initializes the PCI core based on the configuration of the PCI core.
• After the above initialization is completed, start the read-write access test of BAR.

2.2 simulation results

Here, Modelsim is used for simulation analysis.

After the simulation is completed, you can click [project name] [project name]. SIM \ sim_ 1 \ in the simulate.log file in the behav folder, you can view some messages printed during the simulation:

# Running default test ...... # [ 0] : System Reset Asserted... # [ 4995000] : System Reset De-asserted... # [ 64025511] : Transaction Reset Is De-asserted... # [ 65025384] : Transaction Link Is Up... # [ 65057284] : TSK_PARSE_FRAME on Transmit # [ 66473286] : TSK_PARSE_FRAME on Receive # [ 69057326] : Check Max Link Speed = 2.5GT/s - PASSED # [ 69057326] : Check Negotiated Link Width = 4x - PASSED # [ 69081328] : TSK_PARSE_FRAME on Transmit # [ 70329322] : TSK_PARSE_FRAME on Receive # [ 73081380] : Check Device/Vendor ID - PASSED # [ 73105380] : TSK_PARSE_FRAME on Transmit # [ 74353380] : TSK_PARSE_FRAME on Receive # [ 77105265] : Check CMPS ID - PASSED # [ 77105265] : SYSTEM CHECK PASSED # [ 77105265] : Inspecting Core Configuration Space... # [ 77129270] : TSK_PARSE_FRAME on Transmit # [ 77953284] : TSK_PARSE_FRAME on Transmit # [ 78361307] : TSK_PARSE_FRAME on Receive # [ 79201284] : TSK_PARSE_FRAME on Receive # [ 81977392] : TSK_PARSE_FRAME on Transmit # [ 82801289] : TSK_PARSE_FRAME on Transmit # [ 83209392] : TSK_PARSE_FRAME on Receive # [ 84049303] : TSK_PARSE_FRAME on Receive # [ 86825284] : TSK_PARSE_FRAME on Transmit # [ 87649322] : TSK_PARSE_FRAME on Transmit # [ 88057284] : TSK_PARSE_FRAME on Receive # [ 88897326] : TSK_PARSE_FRAME on Receive # [ 91673380] : TSK_PARSE_FRAME on Transmit # [ 92497270] : TSK_PARSE_FRAME on Transmit # [ 92905380] : TSK_PARSE_FRAME on Receive # [ 93745265] : TSK_PARSE_FRAME on Receive # [ 96521284] : TSK_PARSE_FRAME on Transmit # [ 97345392] : TSK_PARSE_FRAME on Transmit # [ 97753284] : TSK_PARSE_FRAME on Receive # [ 98593408] : TSK_PARSE_FRAME on Receive # [ 101369290] : TSK_PARSE_FRAME on Transmit # [ 102193284] : TSK_PARSE_FRAME on Transmit # [ 102601364] : TSK_PARSE_FRAME on Receive # [ 103441284] : TSK_PARSE_FRAME on Receive # [ 106217322] : TSK_PARSE_FRAME on Transmit # [ 107041380] : TSK_PARSE_FRAME on Transmit # [ 107449322] : TSK_PARSE_FRAME on Receive # [ 108289380] : TSK_PARSE_FRAME on Receive # [ 111041269] PCI EXPRESS BAR MEMORY/IO MAPPING PROCESS BEGUN... # BAR 0: VALUE = 00000000 RANGE = ffffe000 TYPE = MEM32 MAPPED # BAR 1: VALUE = 00000000 RANGE = 00000000 TYPE = DISABLED # BAR 2: VALUE = 00000000 RANGE = 00000000 TYPE = DISABLED # BAR 3: VALUE = 00000000 RANGE = 00000000 TYPE = DISABLED # BAR 4: VALUE = 00000000 RANGE = 00000000 TYPE = DISABLED # BAR 5: VALUE = 00000000 RANGE = 00000000 TYPE = DISABLED # EROM : VALUE = 00000000 RANGE = 00000000 TYPE = DISABLED # [ 111041269] : Setting Core Configuration Space... # [ 111065277] : TSK_PARSE_FRAME on Transmit # [ 111889284] : TSK_PARSE_FRAME on Transmit # [ 112297271] : TSK_PARSE_FRAME on Receive # [ 112713380] : TSK_PARSE_FRAME on Transmit # [ 113129284] : TSK_PARSE_FRAME on Receive # [ 113537290] : TSK_PARSE_FRAME on Transmit # [ 113945411] : TSK_PARSE_FRAME on Receive # [ 114361284] : TSK_PARSE_FRAME on Transmit # [ 114769303] : TSK_PARSE_FRAME on Receive # [ 115185322] : TSK_PARSE_FRAME on Transmit # [ 115593284] : TSK_PARSE_FRAME on Receive # [ 116009380] : TSK_PARSE_FRAME on Transmit # [ 116417326] : TSK_PARSE_FRAME on Receive # [ 116833284] : TSK_PARSE_FRAME on Transmit # [ 117241380] : TSK_PARSE_FRAME on Receive # [ 117657284] : TSK_PARSE_FRAME on Transmit # [ 118065265] : TSK_PARSE_FRAME on Receive # [ 118889284] : TSK_PARSE_FRAME on Receive # [ 125657292] : Transmitting TLPs to Memory 32 Space BAR 0 # [ 125681289] : TSK_PARSE_FRAME on Transmit # [ 125785277] : TSK_PARSE_FRAME on Transmit # [ 126993313] : TSK_PARSE_FRAME on Receive # [ 129761284] : Test PASSED --- Write Data: 01020304 successfully received # [ 129841285] : Finished transmission of PCI-Express TLPs # Test Completed Successfully # ** Note: $finish : ../../../imports/sample_tests1.vh(325) # Time: 129841285 ps Iteration: 6 Instance: /board/RP/tx_usrapp # 1 # Break in Module pci_exp_usrapp_tx at ../../../imports/sample_tests1.vh line 325

2.2.1 task description used

First, you need to know about PIO_ writeReadBack_ The functions of some basic subtasks called by Test0 are shown in [PG054] 7 Series Integrated Block for PCI Express IP core learning In section 2.6.1 TPI task list of root port model in, some are introduced, and others can be found in PG054.
Among them, the main tasks and functions are roughly described as follows:

taskexplainTSK_TX_TYPE0_CONFIGURATION_READConfigure 0 read request; The size of TLP header is 3 double word s; No dataTSK_TX_TYPE1_CONFIGURATION_READConfigure 1 read request; The size of TLP header is 3 double word s; No dataTSK_TX_TYPE0_CONFIGURATION_WRITEConfigure 0 write request; The size of TLP header is 3 double word s; With dataTSK_TX_TYPE1_CONFIGURATION_WRITEConfigure 1 write request; The size of TLP header is 3 double word s; With data

TSK_TX_TYPE0_CONFIGURATION_READ(tag_,reg_addr_,first_dw_be_) Header byte0-7: trn_td <= #(Tcq){ 1'b0, 2'b00, 5'b00100, 1'b0, 3'b000, 4'b0000, 1'b0, 1'b0, 2'b00, 2'b00, 10'b0000000001, // 32 REQUESTER_ID, //COMPLETER_ID_CFG, tag_, 4'b0000, first_dw_be_ // 64 }; Header byte8-15: trn_td <= #(Tcq){ COMPLETER_ID_CFG, 4'b0000, reg_addr_[11:2], 2'b00, 32'b0 };

The format of configuration request message header is:

Control TSK_TX_TYPE0_CONFIGURATION_READ task and the corresponding configuration request header format, we will know the meaning of the specific request. Taking this task as an example, it shows that the analysis methods of other tasks are similar.

• REQUESTER_ID = 16'b0000_0001_1010_1111;,tag_:

The non posted request needs to be answered by the completion message to end a completed data transmission. If the sender does not receive the completion message, the tag cannot be used again until the request of the tag ends.

• first_dw_be_: First, we can see TSK_ TX_ TYPE0_ CONFIGURATION_ In the message given by the read task, the length field is 10'b0000000001, indicating the length of data to be read from the target device data area, in DW. The 1st DW BE field corresponds to the first_dw_be_， Is the mask of payload data, and the corresponding bit is 1, indicating that the corresponding byte is valid.

2.2.2 PCIe configuration space

The PCIe configuration space consists of three main parts:

1. Traditional PCI V3.0 type 0 / 1 configuration space header: 0x00~0x3F

   • Type 0 PCI configuration space header (configuration space of PCI Agent device)
     

   • Type 1 PCI configuration space header (configuration space of PCI bridge)
     

2. Traditional expanded configuration space: 0x40~0xFF

   • PCIe Capability
   • Power Management Capability
   • Message Signaled Interrupt (MSI) Capability
   • MSI-X Capability(optional)

3. PCIe extended configuration space: 0x100~0xFFF

   • Device Serial Number Extended Capability Structure (optional)
   • Virtual Channel Extended Capability Structure (optional)
   • Vendor Specific Extended Capability Structure (optional)
   • Advanced Error Reporting Extended Capability Structure (optional)
   • Resizable BAR Extended Capability Structure (optional)

2.2.2 simulation execution process analysis:

1. pci_exp_usrapp_tx related initialization

You can see that the first two messages are to execute pci_exp_usrapp_tx is issued during the related initialization process, indicating that the name of the executed task is .

1. pio_writeReadBack_test0.line6: set board.rp.rx_ usrapp.sim_ The value of timeout is 10050.

1. line8: TSK_SYSTEM_INITIALIZATION

• Wait for the completion of transaction layer reset, and then output the message "transaction reset is de asserted..."
• Wait for the transaction layer link to be established, and then output the message "Transaction Link Is Up..."
• Check the relevant settings in the IP core generator, including Max link speed / width, device / vendor ID and CMPs

Check Link Speed/Width:

• TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12’h70, 4’hF); // If the sending tag is 0, the register address is 12'h70, and the Register Number is 10'h1c (because they are all 32-bit registers, the corresponding address of the Register Number is 10 bits higher), first_dw_be_ Type 0 PCI Express Config Read TLP for 4 'b1111.

Find the PCIe standard. The register name corresponding to the PCIe configuration space address 12'h70 is: Link Status(31:16) Link Control(15:0)

• TSK_WAIT_FOR_READ_DATA: wait for the arrival of packet return data.

The general path of receiving data is pci_exp_usrapp_rx received data - > board.rp.com_ usrapp.TSK_ READ_ Data process data - > the received data is stored in board.rp.com in bytes_ usrapp.frame_ store_ RX [board. Rp.com_usrapp. frame_store_rx_idx], where the pointer frame_ store_ rx_ IDX increases with the data received - > board.rp.com_ usrapp.TSK_ PARSE_ Frame parses this frame data. TSK is executed first_ DECIPHER_ Frame parses this frame and outputs FMT, F_ type, traffic_ Class, TD, EP, attr, len gt h and other information, and then execute TSK_3DW task further parses according to the parsed information, and then executes board.RP.tx_usrapp.TSK_SET_READ_DATA passes the parsed data to tx_app, in TX_ The data received in usrapp is stored in register P_READ_DATA.

• Finally, compare the received data to see what kind of Link Speed/Width it is

You can see P_READ_DATA=32’h10410000=32’b00010000_01000001_00000000_00000000.
Link Status Register.Current Link Speed field = P_READ_DATA[19:16] = 4’b0001. Therefore, the message "Check Max Link Speed = 2.5GT/s - PASSED" is output.

Link Status Register.Negotiated Link Width field = P_READ_DATA[23:20] = 4’b0100. Therefore, the message "check proposed link width = 4x - passed" is output.

Checking the Check Device/Vendor ID is similar to checking the analysis process of CMPS, which will not be repeated here.

1. line10: TSK_BAR_INIT

• TSK_BAR_SCAN: scan the configuration register of the PCIe core.
  PCI via PCIe fabric interface_ Mask writes bar space to find the range.

PCI bus specification specifies the standard implementation method of acquiring BAR space. The step is to write 1 to the BAR register first, and then read the contents of the BAR register to obtain the size of the BAR space. PCIe compatible with PCI.

Therefore, we can see that this task writes p to 12'h10 (BAR0), 12'h14 (BAR1), 12'h18 (BAR2), 12'h1C (BAR3), 12'h20 (BAR4), 12'h24 (BAR5) and 12'h30 (ROM BAR) respectively_ ADDRESS_ Mask (32'hffff_ffff), then read the content of bar, that is, the range, and save it to the register BAR_INIT_P_BAR_RANGE:

Of course, it is consistent with the parameters we set:

• TSK_BUILD_PCIE_MAP: view the range value from the configuration space and establish the corresponding mem/io mapping.

You can see that the register bar is updated according to some information read here_ INIT_ P_ BAR_ Enabled to assign a value. The meaning of this register corresponding to each bar is:

valuemeaning0disable1bar is io mapped2bar is mem32 mapped3bar is mem64 mapped

• TSK_DISPLAY_PCIE_MAP: Based on slave PCI_ The range value read by e device is displayed.

Message line47~53:

• TSK_BAR_PROGRAM: the configuration register of the configured PCIe core.

1. line16~194: read / write test of BAR mapping space

First, judge whether BAR is enabled, and then judge the mapping method of BAR.

• TSK_TX_MEMORY_WRITE_32:

To board.RP.tx_usrapp.BAR_INIT_P_BAR[board.RP.tx_usrapp.ii][31:0]+8'h10, that is, write = in 8'h10.

• TSK_TX_MEMORY_READ_32:

Read the data of this address and compare it. If the message "Test PASSED - Write Data: 01020304 successfully received" is always output.

The whole simulation process is like this.

//Every time you set up an array to have a good look, you are always interrupted. It takes so long to finally analyze it. Through this simulation, you can well understand the relevant knowledge of PCIe. Including transaction types, BAR configuration and analysis, etc., is a very good process.

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