(21)UVM virtual sequence

UVM virtual sequence In the previous section, we talked about hierarchical sequence. The next step is virtual sequence. How to distinguish between the virtual sequence and the hierarchical sequence? What they have in common is the coordination of each sequence. The difference between them is that the objects facing the hierarchical sequ ...

Posted on Sat, 20 Nov 2021 11:51:57 -0500 by robvan75

Random constraint, random distribution, random array, etc. - systemverilog

1, Introduction why With the increase of chip size and complexity, directional testing can not meet the needs of verification, and the proportion of randomized verification increases gradually;Directional testing can find defects you think may exist, while random testing can find defects you can't think of;The environmental requirements of ra ...

Posted on Thu, 18 Nov 2021 11:18:49 -0500 by MoombaDS

Interconnection of ports for UVM TLM communication

Connection between PORT and EXPORT As shown in the figure, ABCD has four ports to communicate between A and B, and between C and D. In order to achieve this goal, A connection relationship must be established between A and B and between C and D. otherwise, how does A know to communicate with B rather than with C or D? So be sure to establi ...

Posted on Tue, 16 Nov 2021 04:00:48 -0500 by merrittj

Stopping of process management -2- thread in system Verilog

You need to create a thread in the test platform, and you also need to stop the thread. The disable statement in verilog can be used to stop threads in system verilog. SystemVerilog provides two types of process control methods: wait and disable. A variety of methods commonly used in disable statements include: disable block_name,disable task_n ...

Posted on Sun, 31 Oct 2021 05:01:27 -0400 by _off_axis_