ODDR of FPGA Xilinx primitive call

Record background: Recently, you need to call the ODDR primitive because you want to implement GMI to rgmii. ODDR: Dedicated Dual Data Rate (DDR) Output Register Through ODDR, the two channels of single end data are combined into one channel for output, the upper and lower edges output data at the same time, and the upper edge outputs a channel ...

Posted on Fri, 03 Apr 2020 18:05:44 -0400 by Secondlaw

FPGA implementation of correlation filter tracking algorithm 1

1 Overview At present, many embedded devices need to use target tracking applications, such as missiles (infrared guidance), UAVs (follow shooting), etc., but in view of the small size of embedded devices, low energy consumption, and small computing power, it is necessary to select an appropriate al ...

Posted on Sun, 15 Mar 2020 01:29:09 -0400 by able

An example of nvdla ephon used to generate state machine code automatically

In NVIDIA Deep Learning Accelerator, a python script epython is used. Source code address: https://github.com/nvdla/hw/blob/master/tools/bin/epython  . The full name of ephon is embedded python utility, which is simply used to preprocess python scripts embedded in verilog files. Using the simpl ...

Posted on Thu, 05 Mar 2020 00:26:09 -0500 by Amit Rathi

ZYNQ Custom AXI Bus IP Application-PWM for Respiratory Light Effect

1. Preface In the case of high real-time requirements, the way the CPU software is executed obviously can not meet the requirements, which requires hardware logic to implement some functions.For a custom IP core to be accessed by the CPU, it must have a bus interface.ZYNQ uses AXI BUS to achieve data interaction between PS and PL.This paper tak ...

Posted on Mon, 02 Mar 2020 11:07:16 -0500 by alanrenouf

Verilog implements RAM(6-dual port asynchronous read / write SRAM)

In the previous work, we carried on the noun literacy to the common memory device, realized the simple single port synchronous read-write SRAM by calling the IP core, carried on the Verilog description to the single port synchronous read-write SRAM, carried on the design and the analysis to the singl ...

Posted on Tue, 25 Feb 2020 01:35:33 -0500 by verycleanteeth

The use of ICAP primitives in FPGA -- the implementation of Multiboot function

Use of ICAP primitives First, gossip Introduction of ICAP primitives Introduction of ICAPE2 primitive Code of ICAPE2 primitive Verification Concluding remarks First, gossip I haven't blogged for a while, because I went home from school. Now is the prevalence of pneumonia, not to add trouble to t ...

Posted on Thu, 30 Jan 2020 04:29:49 -0500 by frih

FPGA Foundation (verilog language) - syntax

Introduction to verilog verilog is a language with syntax similar to c, but it is different from c, for example: 1.verilog language is parallel, each always block is executed at the same time, while c language is executed in sequence 2.verilog is also called hardware description language. When programming with verilog, it is better to describe ...

Posted on Sun, 24 Nov 2019 13:49:38 -0500 by andygrant

socket programming based on UDP protocol

Catalog Simple example of UDP socket Server side Client UPD socket non stick package problem Server side Client qq chat Server side Client 1 Client 2 Operation result Simple example of UDP socket Server side import socket serv ...

Posted on Sat, 02 Nov 2019 02:12:18 -0400 by dsoftnet

master reading and writing design based on AHB bus (Verilog)

I. AHB bus learning 1. AHB bus structure             As shown in the figure, the AHB bus system uses the central multi-channel selection mechanism to realize the interconnection between the master and the slave. As can be seen from the figure, AHB bus structure can be divided into three parts: host, slave and control. The control part consi ...

Posted on Mon, 21 Oct 2019 05:42:11 -0400 by quark76

Realization of Traffic Signal Light by Verilog

In the course design of sophomore's digital circuit, Xilinx FPGA was used to implement simple traffic lights for a daily assignment, but unfortunately the time was limited and could not be completed finally. Just in this semester, SOPC design course is chosen, and Xilinx FPGA is also used, so we intend to re-complete the relevant content of tra ...

Posted on Sat, 05 Oct 2019 00:35:36 -0400 by zigizal