socket programming based on UDP protocol

Catalog Simple example of UDP socket Server side Client UPD socket non stick package problem Server side Client qq chat Server side Client 1 Client 2 Operation result Simple example of UDP socket Server side import socket serv ...

Posted on Sat, 02 Nov 2019 02:12:18 -0400 by dsoftnet

master reading and writing design based on AHB bus (Verilog)

I. AHB bus learning 1. AHB bus structure             As shown in the figure, the AHB bus system uses the central multi-channel selection mechanism to realize the interconnection between the master and the slave. As can be seen from the figure, AHB bus structure can be divided into three parts: host, slave and control. The control part consi ...

Posted on Mon, 21 Oct 2019 05:42:11 -0400 by quark76

Realization of Traffic Signal Light by Verilog

In the course design of sophomore's digital circuit, Xilinx FPGA was used to implement simple traffic lights for a daily assignment, but unfortunately the time was limited and could not be completed finally. Just in this semester, SOPC design course is chosen, and Xilinx FPGA is also used, so we intend to re-complete the relevant content of tra ...

Posted on Sat, 05 Oct 2019 00:35:36 -0400 by zigizal

How to Write the spyglass_cdc001:sgdc Constraints

1. What is the spyglass cdc sgdc constraint Spyglass is an EDA tool for IC design, which can be used for Verilog code quality checking, power analysis and so on. Verilog quality checks include lint and cdc checks. Lint is mainly used to check g ...

Posted on Sat, 07 Sep 2019 04:32:24 -0400 by spasm37

Implementation of nRF2401 Wireless Module Receiving_FPGA~~

Recently, the capsule endoscopy project has used the wireless transceiver module commonly used in the industry, namely NRF series wireless transceiver module of EnZhiPu Company. There are several options for this module at present. For example, nRF24L01 only has wireless transceiver module, which requires external MCU to drive and transmit data ...

Posted on Tue, 04 Jun 2019 16:52:31 -0400 by DataRater

Implementation of Rising Edge Detector by Two State Machines and Verilog Direct Implementation

Rising edge detection means that when the input signal changes from 0 to 1, an indication signal of a clock cycle is output. The main purpose of this topic is to deepen the impression of edge detection and better understand the implementation mechanism of two state machines (Moore machine and Mealy machine). See the end of the book for source ...

Posted on Wed, 22 May 2019 16:56:39 -0400 by gl_itch

C++ Foundation - Operator Overloading Friend Function Example

I. Preface In fact, the purpose of my study of C++ is to understand OOP design ideas and to prepare for the verification of complex design using System Verilog. If you want to really do some software project-level things, you also need to master other high-level languages and libraries, frameworks and other knowledge. Therefore, this series of ...

Posted on Thu, 16 May 2019 23:09:07 -0400 by s_ainley87

Demonstration of [DE2i-150] Reconstructing PCIe_Fundmental

The following information is mainly to make a memorandum, to avoid forgetting later, by the way, to the people in need. ========================================== This paper mainly refers to the PCie_Fundmental paradigm in E2i-150 disc of Youjing Technology, and then rebuilds a new paradigm program.   1 // ============================== ...

Posted on Thu, 21 Mar 2019 06:12:53 -0400 by willl