(21)UVM virtual sequence

UVM virtual sequence In the previous section, we talked about hierarchical sequence. The next step is virtual sequence...
11:51 20 November 2021

Verilog Implemented Gray Code to Binary Code Conversion

1. What is Gray Code     ...
12:05 3 November 2021

Simulation of alarm mode control for Proteus sensor + gas concentration detection

catalog Simulation of alarm mode control for Proteus sensor + gas concentration detection 1 understanding of experim...
21:57 25 June 2020

An example of nvdla ephon used to generate state machine code automatically

In NVIDIA Deep Learning Accelerator, a python script epython is used. Source code address:
0:26 5 March 2020

ZYNQ Custom AXI Bus IP Application-PWM for Respiratory Light Effect

1. Preface In the case of high real-time requirements, th...
11:07 2 March 2020

Verilog implements RAM(6-dual port asynchronous read / write SRAM)

In the previous work, we carried on the noun literacy to the common memory device, realized the simple single port synch...
1:35 25 February 2020

The use of ICAP primitives in FPGA -- the implementation of Multiboot function

Use of ICAP primitives First, gossip Introduction of ICAP primitives Introduction of ICAPE2 primitive Code of ICAPE2 primitive Verification Concludin...
4:29 30 January 2020

FPGA Foundation (verilog language) - syntax

Introduction to verilog verilog is a language with syntax similar to c, but it is different from c, for example: 1.verilog language is parallel, each ...
13:49 24 November 2019

socket programming based on UDP protocol

Catalog Simple example of UDP socket Server side Client UPD socket non stick package problem Server side Client qq chat Server side Client 1 Client 2...
2:12 2 November 2019